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Data Sheet, Rev. 1.11, April 2005
HYB18T256324F-16 HYB18T256324F-20 HYB18T256324F-22
256-Mbit GDDR3 DRAM [600MHz]
RoHS compliant
Memory Products
Never
stop
thinking.
Edition 04-2005 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Under no circumstances may the Infineon Technologies product as referred to in this data sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Infineon Technologies product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible).
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
HYB18T256324F-16 HYB18T256324F-20 HYB18T256324F-22 Revision History: Previous Revision: Page 2 30 75 79 Rev. 1.11 Rev. 1.0 04-2005
Subjects (major changes since last revision) added disclaimer figure 11: note 1 changed table 41: added currents for -16 table 42-44: new values
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Data Sheet 3 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Table of Contents 1 1.1 1.2 2 2.1 2.2 2.3 2.3.1 2.3.2 2.4 2.4.1 2.4.2 2.4.3 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.6 3.7 3.7.1 3.7.2 3.7.3 3.7.3.1 3.7.3.2 3.7.4 3.7.5 3.7.6 3.7.7 3.7.8 3.8 3.8.1 3.8.2 3.8.3 3.8.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Diagram and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Diagram for One Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Table for more than one Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Table for CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks, CKE, Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable impedance output drivers and active terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . GDDR3 IO Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Calibration for Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Switching of DQ terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output impedance and Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Set Command (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination Rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vendor Code and Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank / Row Activation (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write - Consecutive Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge followed by Read / Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . Write followed by Precharge on same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive Read Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11 12 14 15 15 16 19 19 20 21 22 22 23 24 24 25 26 27 28 29 29 29 29 30 30 31 32 32 33 33 33 33 34 35 35 38 39 39 40 41 42 43 44 45 46 46 48 49 49
Data Sheet
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
3.8.3.2 3.8.3.3 3.8.4 3.8.5 3.8.6 3.9 3.9.1 3.9.2 3.10 3.11 3.12 3.12.1 3.12.2 3.13 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.7.1 4.8 4.9 4.10 4.11 4.11.1 4.12 4.13 4.14 5 5.1
Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Precharge on the same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Termination Disable (DTERDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge (PRE/PREALL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Refresh Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Entry (SREFEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Exit (SREFEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power & DC Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Logic Input Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Clock DC and AC Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver IV characteristics at 40 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of timing parameters for -1.6, -2.0 and -2.2 ns speed sorts in DLL on mode . . . . . . . . . AC Characteristics and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 51 52 53 54 55 57 58 59 61 62 62 63 64 65 65 66 67 67 68 68 69 69 70 71 72 73 73 73 75 77
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Sheet
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Rev. 1.11, 04-2005 10292004-DOXT-FS0U
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Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47
Key Timing and Power Supply Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent Autoprecharge 18 Function Truth Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Function Truth Table II (CKE Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General Timing Parameters for -1.6, -2.0 and -2.2 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Range of external resistance ZQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Termination types and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Termination update Keep Out time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Number of Legs used for Terminator and Driver Self Calibration . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 EMRS Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision ID and Vendor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Vendor Code and Revision ID Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . 30 MRS Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ACT Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Mapping of WDQS and DM signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 WR Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 WL / CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 READ Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 47 BA1, BA0 precharge bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Precharge Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . 60 Autorefresh Timing Parameters for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . 61 Self Refresh Exit Timing Parameter for -1.6, -2.0 and -2.2 speed sorts. . . . . . . . . . . . . . . . . . . 63 Power Down Exit Timing Parameter for -1.6, -2.0 and -2.2 speed sorts . . . . . . . . . . . . . . . . . . 64 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Differential Clock DC and AC Input conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Programmed Driver IV Characteristics at 40 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Programmed Terminator Characterisitc at 60 Ohm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Programmed Terminator Characterisitics at 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Programmed Terminator Characterisitc at 240 Ohm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Operating Current Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Timing Parameters for -1.6, -2.0 and -2.2 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 HYB18T256324F-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HYB18T256324F-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HYB18T256324F-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 P-FBGA 144 Package Thermal Resitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Sheet
6
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55
Standard Ballout 256-Mbit GDDR3 DRAM [600MHz]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State diagram for one bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock, CKE and Command/Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Driver simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Termination update keep out time after Autorefresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Calibration of PMOS and NMOS Legs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT Disable Timing during a READ command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing of Vendor Code and Revision ID generation on DQ[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activating a specific row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Activation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Write Burst / DM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Burst Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Write Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive Write Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank . . . . . Write followed by Precharge on same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Read Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gapless Consecutive Read Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive Read Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read followed by Precharge on the same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Termination Disable Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS Command followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTERDIS Command followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Refresh Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Exit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Ohm Driver Pull-Down and Pull-Up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 14 19 22 23 24 25 26 27 28 28 29 30 31 31 32 34 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 55 56 57 58 59 60 61 61 62 62 63 63 64 64 68 69 70
Data Sheet
7
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Figure 56 Figure 57 Figure 58
120 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Package Outline FBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Data Sheet
8
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
256-Mbit GDDR3 DRAM [600MHz]
HYB18T256324F-16 HYB18T256324F-20 HYB18T256324F-22
1
1.1
* * * * * * * * * * * *
Overview
Features
* * * * * * * * * * Single ended READ strobe (RDQS) per byte. RDQS edge-aligned with READ data Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data DLL aligns RDQS and DQ transitions with Clock Programmable IO interface including on chip termination (ODT) Autoprecharge option with concurrent autoprecharge support 4K Refresh (32ms) Autorefresh and Self Refresh P-TBGA 144 package (11mm x 11mm) VDD / VDDQ Voltage (according to Table 1) Calibrated output drive. Active termination support.
Maximum clock frequency of 600 MHz Organization: 2048K x 32 x 4 banks 4096 rows and 512 columns (128 burst start locations) per bank Differential clock inputs (CLK and CLK) CAS latencies of 5, 6 and 7 Write latencies of 2, 3, 4 Fixed burst sequence with length of 4. 4n prefetch Short RAS to CAS timing for Writes tRAS Lockout support tWR programmable for Writes with Auto-Precharge Data mask for write commands
Table 1 Speed Sort
Key Timing and Power Supply Parameters -1.6 - 2.0 2.0 100 mV 2.0 500 2.0 500 -- -- -0.4 0.4 0.225 - 2.2 2.0 100 mV 2.2 455 2.2 455 2.7 370 -0.45 0.45 0.25 Units V ns MHz ns MHz ns MHz ns ns ns
Power Supply CAS latency = 7 CAS latency = 6 CAS latency = 5 Access Time RDQS-DQ Skew
VDD / VDDQ tCK7 min fCK7 max tCK6 min fCK6 max tCK5 min fCK5 max tACmin tACmax tDQSQ
2.0 100 mV 1.6 600 2.0 500 -- -- -0.4 0.4 0.225
Data Sheet
9
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Overview
Table 2
Ordering Information Organisation x32
Part Number1) HYB18T256324F-16 HYB18T256324F-20 HYB18T256324F-22
VDD / VDDQ (V)
2.0 2.0 2.0
Clock (MHz) Package 600 500 455 P-TBGA 144
1) HYB: designator for memory components 256: 256-Mbit density 32: 32 bit interface 4: Die Revision F: Green Product
1.2
General Description
Read and write accesses to the HYB18T256324F- [16/20/22] are burst oriented. The burst length is fixed to 4 and the two least significant bits of the burst address are 'Don't Care' and internally set to LOW. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 4 banks consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and WRITE to provide a selftimed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of the HYB18T256324F-[16/20/22] allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. The device is supplied with 2.0 V for output drivers and core. (VDD / VDDQ voltages see Table 1) The "On Die Termination" interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register. The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (autocalibration) or to 35, 40 or 45 Ohms. Auto Refresh and Power Down with Self Refresh operations are supported. A standard P-TBGA 144 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former DDR Graphics SDRAM products.
The Infineon 256-Mbit GDDR3 DRAM [600MHz]is a high speed memory device, designed for high bandwidth intensive applications like PC graphics systems. The chip's quad bank architecture is optimized for high speed and achieves a peak bandwidth of 8 Gbyte/s using a 32 bit interface and a maximum system clock of 600 MHz. HYB18T256324F-[16/20/22] uses a double data rate interface and a 4n-prefetch architecture. The GDDR3 interface transfers two 32 bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4nprefetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, onehalf-clock-cycle data transfers at the I/O pins. Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are centeraligned with data for write commands. The HYB18T256324F-[16/20/22] operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to both edges of RDQS. In this document references to 'the positive edge of CLK' imply the crossing of the positive edge of CLK and the negative edge of CLK. Similarly, the 'negative edge of CLK' refers to the crossing of the negative edge of CLK and the positive edge of CLK. References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar fashion.
Data Sheet
10
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration
2
Pin Configuration
Figure 1
Standard Ballout 256-Mbit GDDR3 DRAM [600MHz]
Note: Figure shows top view
Data Sheet
11
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration
2.1
Table 3 Ball CLK, CLK
Ball Definition and Description
Ball description Type Input Detailed Function Clock: CLK and CLK are differential clock inputs. Address and command inputs are latched on the positive edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are referenced to CLK. CLK and CLK are not internally terminated. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock and input buffers. Taking CKE LOW provides Power Down. If all banks are precharged, this mode is called Precharge Power Down and Self Refresh mode is entered if a Autorefresh command is issued. If at least one bank is open, Active Power Down mode is entered and no Self Refresh allowed. All input receivers except CLK, CLK and CKE are disabled during Power Down. In Self Refresh mode the clock receivers are disabled too. Self Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power Down without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK. The value of CKE is latched asynchronously by Reset during Power On to determine the value of the termination resistor of the address and command inputs. CKE is not allowed to go LOW during a RD, a RW or a snoop BURST. Chip Select: CS enables the command decoder when low and disables it when high. When the command decoder is disabled, new commands with the exeption of DETERNIS are ignored, but internal operations continue. CS is one of the four command balls. Command Inputs: Sampled at the positive edge of CLK, CAS, RAS, and WE define (together with CS) the command to be executed. Data Input/Output: The DQ signals form the 32 bit data bus. During READs the balls are outputs and during WRITEs they are inputs. Data is transferred at both edges of RDQS. Input Data Mask: The DM signals are input mask signals for WRITE data. Data is masked when DM is sampled HIGH with the WRITE data. DM is sampled on both edges of WDQS. DM0 is for DQ<0:7>, DM1 is for DQ<8:15>, DM2 is for DQ<16:23> and DM3 is for DQ<24:31>. Although DM balls are input-only, their loading is designed to match the DQ and WDQS balls.
CKE
Input
CS
Input
RAS, CAS, WE DQ<0:31> DM<0:3>
Input I/O Input
RDQS<0:3>
Output Read Data Strobes: RDQSx are unidirectional strobe signals. During READs the RDQSx are transmitted by the Graphics SDRAM and edge-aligned with data. RDQS have preamble and postamble requirements. RDQS0 is for DQ<0:7>, RDQS1 for DQ<8:15>, RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>. Write Data Strobes: WDQS are unidirectional strobe signals. During WRITEs the WDQS are generated by the controller and center aligned with data. WDQS have preamble and postamble requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for DQ<16:23> and WDQS3 for DQ<24:31>. Bank Address Inputs: BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED MODE REGISTER SET commands. Address Inputs: During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is precharged (selected by BA<0:1>, A8 LOW) or all 4 banks are precharged (A8 HIGH). During (EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are sampled with the positive edge of CLK. ODT Impedance Reference: The ZQ ball is used to control the ODT impedance.
WDQS<0:3> Input
BA<0:1>
Input
A<0:11>
Input
ZQ
-
Data Sheet
12
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration Table 3 Ball RES Ball description Type Input Detailed Function Reset pin: The RES pin is a VDDQ CMOS input. RES is not internally terminated. The LOW to HIGH transition of the Reset signal is used to latch the CKE value during Power On in order to set the value of the termination resistors of the address and command inputs. When RES is LOW, all terminations are switched off. The LOW to HIGH transition of the RES signal must occur at the beginning of the power up sequence in order to insure functionnality.
Vref VDD, VSS VDDQ, VSSQ
NC, RFU
Supply Voltage Reference: Vref is the reference voltage input. Supply Power Supply: Power and Ground for the internal logic. Supply I/O Power Supply: Isolated Power and Ground for the output buffers to provide improved noise immunity. Please do not connect No Connect and Reserved for Future Use balls.
Data Sheet
13
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration
2.2
Functional Block Diagram
A0-A7,A9, A8/AP, A10-A11 BA0, BA1
Address buffer
A8/AP
Row Addresses A0-A11, BA0-BA1
Column Addresses A2-A7,A9
CS# Sense Amplifiers and Data Bus Buffer Sense Amplifiers and Data Bus Buffer Sense Amplifiers and Data Bus Buffer CAS# WE# RES Sense Amplifiers and Data Bus Buffer Control Logic & Timing Generator RAS# Row Decoder Memory Array Bank 0 Row Decoder Memory Array Bank 1 Row Decoder Memory Array Bank 2 Row Decoder Memory Array Bank 3
Mode Register
Refresh Counter
Row Address Buffer
Column Address Buffer
Column Decoder
Column Decoder
Column Decoder
4096 x 512 x 32 bit
4096 x 512 x 32 bit
4096 x 512 x 32 bit
Column Decoder
4096 x 512 x 32 bit
ZQ
CKE CLK CLK# DLL Output Buffers Input Buffers
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
Data RDQS0 WDQS0 DM0
Data RDQS1 WDQS1 DM1
Data RDQS2 WDQS2 DM2
Figure 2
Functional Block Diagram
Data Sheet
14
Data RDQS3 WDQS3 DM3
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration
2.3 2.3.1
Commands Command Table
In the following table CKEn refers to the positive edge of CLK corresponding to the clock cycle when the command is given to the Graphics SDRAM. CKEn-1 refers to the previous positive edge of CLK. For all command and address inputs CKEn is implied. All input states or sequences not shown are illegal or reserved. Table 4 Operation Device Deselect Command Overview Code DESEL CKE CKE CS n-1 n H H H RAS CAS WE L X H H H L L L H H H H L L L X H X L X X X H L H L L H L L L L H H L X H X L X X L H H H L L H H H L L L L H X H X H X BA0 BA1 A8 X X X A2-7 Note A9-11 X 1
Data Terminator Disable No Operation Mode Register Set Extended Mode Register Set Bank Activate Read Read w/ Autoprecharge Write Write w/ Autoprecharge Precharge Precharge All Auto Refresh Power Down Mode Entry Power Down Mode Exit Self Refresh Entry Self Refresh Exit
DTERDIS H NOP MRS EMRS ACT RD RD/A WR WR/A PRE PREALL AREF H H H H H H H H H H H
H H H H H H H H H H H H L H L H
H L L L L L L L L L L L H L X L X
X X 0 1 BA BA BA BA BA BA X X X X X X
X X 0 0 BA BA BA BA BA BA X X X X X X
X X
X X
1,9
OPCODE OPCODE Row Address L H L H L H X X X X X Col. Col. Col. Col. X X X X X X X 1,2 1,3 1,3 1,3 1,3 1 1 1,4 1,5 1,6 1,7 1,8
PWDNEN H PWDNEX L SREFEN SREFEX H L
1. X represents "Don't Care". 2. BA0 and BA1 provide bank address, A0 - A11 provide the row address. 3. BA0 and BA1 provide bank address, A2- A7, A9 provide the column address, A8/AP controls Auto Precharge. 4. Auto Refresh and Self Refresh Entry differ only by the state of CKE 5. PWDNEN is selected by issuing a DESEL or NOP at the first positive CLK edge following the HIGH to LOW transition of CKE. 6. First possible valid command after tXPN. During tXPN only NOP or DESEL commands are allowed.
7. Self Refresh is selected by issuing AREF at the first positive CLK edge following the HIGH to LOW transition of CKE. 8. First possible valid command after tXSC. During tXSC only NOP or DESEL commands are allowed. 9. This command is invoked when a Read is issued on another DRAM rank placed on the same command bus. Cannot be in power-down or self-refresh state. The Read command will cause the data termination to be disabled. Refer to for timing. Abbreviations: BA:Bank Address Col.:Column Address 15 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
Data Sheet
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration
2.3.2
Table 5 Command DESEL NOP
Description of Commands
Description of Commands Description The DESEL function prevents new commands from being executed by the Graphics SDRAM. The Graphics SDRAM is effectively deselected. Operations in progress are not affected. The NOP command is used to perform a no operation to the Graphics SDRAM, which is selected (CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. The Mode Register is loaded via address inputs A0 - A11. For more details see sections Chapter 3.5. The MRS command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. The Extended Mode Register is loaded via address inputs A0 - A11. For more details see section Chapter 3.4. The EMRS command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. The ACT command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the address provided in inputs A0 - A11 selects the row. This row remains active (or open) for accesses until a precharge (PRE, RD/A, or WR/A command) is issued to that bank. A precharge must be issued before opening a different row in the same bank. The RD command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The row will remain open for subsequent accesses. For RD commands the value on A8 is set LOW. The RD/A command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end of the read burst. The same individual-bank precharge function is performed like it is described for the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. The user must not issue a new ACT command to the same bank until the precharge time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the earliest possible time as described in section Chapter 3.10. The WR command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The row will remain open for subsequent accesses. For WR commands the value on A8 is set LOW. Input data appearing on the DQs is written to the memory array depending on the value on the DM input appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed for that byte / column location. The WR/A command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end of the write burst. The same individual-bank precharge function is performed which is described for the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. The user is not allowed to issue a new ACT to the same bank until the precharge time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the earliest possible time as described in section Chapter 3.7. Input data appearing on the DQs is written to the memory array depending on the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. 16 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
MRS
EMRS
ACT
RD
RD/A
WR
WR/A
Data Sheet
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration Table 5 Command PRE Description of Commands Description The PRE command is used to deactivate the open row in a particular bank. The bank will be available for a subsequent row access a specified time (tRP) after the PRE command is issued. Inputs BA0 and BA1 select the bank to be precharged. A8/AP is set to LOW. Once a bank has been precharged, it is in the idle state and must be activated again prior to any RD or WR commands being issued to that bank. A PRE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. The PREALL command is used to deactivate all open rows in the memory device. The banks will be available for a subsequent row access a specified time (tRP) after the PREALL command is issued. Once the banks have been precharged, they are in the idle state and must be activated prior to any read or write commands being issued. The PREALL command will be treated as a NOP for those banks where there is no open row, or if a previously open row is already in the process of precharging. PREALL is issued by a PRE command with A8/AP set to HIGH. The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory content. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AREF command. The HYB18T256324F-[16/20/22] requires AREF cycles at an average periodic interval of tREFI(max)=7.8s. To improve efficiency a maximum number of eight AREF commands can be posted to one memory device (with tRFC from AREF to AREF) as described in section Chapter 3.11. This means that the maximum absolute interval between any AREF command is 8 x 7.8s (62.4s). This maximum absolute interval is to allow the GDDR3 Graphics RAM output drivers and internal terminators to recalibrate, compensating for voltage and temperature changes. All banks must be in the idle state before issuing the AREF command. They will be simultaneously refreshed and return to the idle state after AREF is completed. tRFC is the minimum required time between an AREF command and a following ACT/AREF command. The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest of the system is powered down. When entering the self refresh mode by issuing the SREFEN command, the GDDR3 Graphics RAM retains data without external clocking. The SREFEN command is initiated like an AREF command except CKE is disabled (LOW). The DLL is automatically disabled upon entering Self Refresh mode and automatically enabled and reset upon exiting Self Refresh. (200 cycles must then occur before a RD command can be issued) The adress, command and data terminators remain on input signals except CKE are "Don't Care". If two GDDR3 Graphics RAMs share the same cimmand and address bus, Self Refresh max be entered only for the two devices at the sme time. The SREFEX command is used to exit the self refresh mode. The DLL is automatically enabled and resetted upon exiting. The procedure for exiting self refresh requires a sequence of commands. First CLK and CLK must be stable prior to CKE going from LOW to HIGH. Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXSNR is satisfied. This time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and output calibration is to apply NOPs for 200 cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. The PWDNEN command enables the power down mode. It is entered when CKE is set low together with a NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power consumption. The DLL remains active (unless disabled before with EMRS). All banks can be set to idle state or stay active. During Power Down Mode, refresh operations cannot be performed; therefore the refresh conditions of the chip have to be considered and if necessary Power Down state has to be left to perform an Autorefresh cycle.
PREALL
AREF
SREFEN
SREFEX
PWDNEN
Data Sheet
17
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration Table 5 Command PWDNEX Description of Commands Description A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode. Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXPN is satisfied. After tXPN any command can be issued, but it has to comply with the state in which the power down mode was entered. Data Termination Disable (Bus snooping for RD commands) : The Data Termination Disable Command is detected by the device by snooping the bus for RD commands excluding CS. The GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration is 4 clocks. In a two rank system, both DRAM devices will snoop the bus for RD commands to either device and both will disable their terminators if a RD command is detected. The command and address terminators are always enabled. See Figure 9 for an example of when the data terminators are disabled during a RD command. Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent Autoprecharge To Command RD or RD/A WR or WR/A PRE ACT RD/A RD or RD/A WR or WR/A PRE ACT Minimum delay to another bank (with concurrent autoprecharge) (WL + 2) . tCK + tWTR 2 . tCK tCK tCK 2 . tCK (CL + 4 - WL) . tCK tCK tCK Note
DTERDIS
Table 6
From Command WR/A
Data Sheet
18
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration
2.4 2.4.1
State Diagram and Truth Tables State Diagram for One Activated Bank
The following diagram shows all possible states and transitions for one activated bank. The other three banks of the Graphics SDRAM are assumed to be in idle state.
single bank
WR
ACTIVE
PRE WR/A RD/A PDEN PDEX
RD
ACT
MRS EMRS
IDLE
AUTO REFRESH SREX SREN
PDEN PDEX
active
POWER DOWN
precharge
SELF REFRESH
all banks
Figure 3 State diagram for one bank
Note: MRS, EMRS, AUTO REFRESH, SELF REFRESH and precharge POWER DOWN are only allowed if all four banks are idle.
Data Sheet
19
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration
2.4.2
Function Truth Table for more than one Activated Bank
submitted command. This table is based on the assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD, tRTW and tWTR have to be taken always into account.
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the chip's multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions are illegal. Notes 1-11 define the start and end of the actions belonging to a Table 7 Current State ACTIVE Function Truth Table I ongoing action on bank n ACTIVATE 1 WRITE 2 WRITE/A 3 READ 4 READ/A 5 PRECHARGE 6 PRECHARGE ALL 6 POWER DOWN ENTRY 7 IDLE ACTIVATE
1 7
possible action in parallel on bank m ACT, PRE, WRITE, WRITE/A, READ, READ/A 12 ACT, PRE, WRITE, WRITE/A, READ, READ/A13 ACT, PRE, WRITE, WRITE/A, READ 14 ACT, PRE, WRITE, WRITE/A, READ, READ/A15 ACT, PRE, WRITE, WRITE/A, READ, READ/A 15 ACT, PRE, WRITE, WRITE/A, READ, READ/A 12 ACT 9
POWER DOWN ENTRY AUTO REFRESH
8
SELF REFRESH ENTRY EXTENDED MRS POWER DOWN SELF REFRESH
9 10
7
MODE REGISTER SET (MRS) POWER DOWN EXIT
-
SELF REFRESH EXIT 11
1. Action ACTIVATE starts with issuing the command and ends after tRCD 2. Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge; exept for READ, READ/A. WRITE, WRITE/A ends tWTR after the first pos. edge of CLK following the last falling WDQS edge. 3. Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge; exept for READ, READ/A. WRITE, WRITE/A ends tWTR after the first pos. edge of CLK following the last falling WDQS edge. 4. Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS 5. Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS 6. Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP Data Sheet 20
7. During POWER DOWN and SELF REFRESH only the EXIT commands are allowed 8. Action AUTO REFRESH starts with issuing the command and ends after tRFC 9. Actions MODE REGISTER SET and EXTENDED MODE REGISTER SET start with issuing the command and ends after tMRD 10. Action POWER DOWN EXIT starts with issuing the command and ends after tXPN 11. Action SELF REFRESH EXIT starts with issuing the command and ends after tXSC 12. During action ACTIVATE an ACT command on another bank is allowed considering tRRD, a PRE command on another bank is allowed any time. WR, WR/A, RD and RD/A are always allowed. 13. During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR is met.
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Pin Configuration 14. During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank has to be separated by at least one NOP from the ongoing command. RD is not allowed before tWTR is met. RD/A is not allowed during an ongoing WRITE/A action. 15. During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to meet tRTW.
2.4.3
Table 8 CKE n-1 L L H
Function Truth Table for CKE
Function Truth Table II (CKE Table) CKE n L H L CURRENT STATE Power Down Self Refresh Power Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle COMMAND X X DESEL or NOP DESEL or NOP DESEL or NOP DESEL or NOP Auto Refresh ACTION stay in Power Down stay in Self Refresh Exit Power Down Exit Self Refresh 5 Entry Precharge Power Down Entry Active Power Down Entry Self Refresh 4. All states and sequences not shown are illegal or reserved. 5. DESEL or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum of 200 clock cycles is required before applying any other valid command.
1. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the GDDR3 Graphics RAM immediatly prior to clock edge n. 3. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND.
Data Sheet
21
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3
3.1
Functional Description
Clocks, CKE, Commands and Addresses
Figure 4
Clock, CKE and Command/Address Timings
Setup and Hold Timing for CKE is equal to CMD and ADDR Setup and Hold Timing. The DLL ensures the alignment of DQs and CLK. Therefore the preferred operation mode for high frequencies is DLL on. The DLL frequency range is from 600 MHz down to 250 MHz. Table 9 Parameter General Timing Parameters for -1.6, -2.0 and -2.2 speed sorts CAS Symbol latency min Clock Clock Cycle Time 7 6 5 System frequency 7 6 5 Clock high level width Clock low-level width Address/Command/CKE input setup time Address/Command/CKE input pulse width Limit Values -1.6 max 3.3 3.3 -- 600 500 -- 0.55 0.55 -- -- -- min 2.0 2.0 -- 250 250 -- 0.45 0.45 0.75 0.75 0.85 -2.0 max 4.0 4.0 -- 500 500 -- 0.55 0.55 -- -- -- min 2.2 2.2 2.7 250 250 250 0.45 0.45 0.75 0.75 0.85 -2.2 max 4.0 4.0 4.0 455 455 370 0.55 0.55 -- -- -- ns ns ns MHz MHz MHz Unit
tCK7 tCK6 tCK5 fCK7 fCK6 fCK5 tCH tCL tIS
1.6 2.0 -- 300 300 -- 0.45 0.45 0.6 0.6 0.85
tCK tCK
ns ns
Command, CKE and Address Setup and Hold Times
Address/Command/CKE input hold time tIH
tIPW
tCK
Data Sheet
22
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.2
Initialization
The HYB18T256324F-[16/20/22] must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation or permanent damage to the device. The following sequence is highly recommended for Power-Up: 1. Apply power (VDD, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF. Maintain RES=L and CS=H to ensure that all the DQ ouputs will be in HiZ state, all active terminations off and the DLL off. All other pins may be undefined. 2. Maintain stable conditions for 200 s minimum for the GDDR3 Graphics RAM to power up. 3. After clock is stable, set CKE to L. After tATS minimum set RES to high. On the rising edge of RES, the CKE value is latched to determine the address and command bus termination value. If CKE is sampled LOW the address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination is set to ZQ. 4. After tATH minimum, set CKE to high. 5. Wait a minimum of 350 cycles to calibrate and update the address and command termination impedances. Issue DESELECT on the command bus during these 350 cycles. 6. Apply a PRECHARGE ALL command, followed by an Extended Mode Register command after tRP is met and activate the DLL. 7. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters. 8. Wait 200 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver impedance value. 9. Issue a PRECHARGE ALL command or issue 4 single bank PRECHARGE commands, one to each of the 4 banks to place the chip in an idle state. 10. Issue two or more AUTO REFRESH commands to update the driver impedance.
Figure 5 Table 10 Parameter
Power Up Sequence Reset Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max -- -- 23 min 10 10 Limit Values -2.0 max -- -- min 10 10 -2.2 max -- -- ns ns Unit Notes
RES to CKE setup time RES to CKE hold time Data Sheet
tATS tATH
10 10
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.3 3.3.1
Programmable impedance output drivers and active terminations GDDR3 IO Driver and Termination
DM<0:3>. The two termination values that are selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2. The value of ZQ is also used to calibrate the internal address command termination resistors. The inputs terminated in this manner are A<0:11>, CKE, CS, RAS, CAS, WE. The two termination values that are selectable upon power up (CKE latched a the LOW to HIGH transition of RES) are ZQ/2 and ZQ. The signals RES and CLK/CLK are not internally terminated. If no resistance is connected to ZQ, an internal default value of 240 will be used. In this case, no calibration will be performed.
The GDDR3 SGRAM is equipped with programmable impedance output buffers and active terminations. This allows the user to match the driver impedance to the system impedance. To adjust the impedance of DQ<0:31> and RDQS<0:3> , an external precision resistor (ZQ) is connected between the ZQ pin and VSS. The value of the resitor must be six times the value of the desired impedance. For example, a 240 resistor is required for an output impedance of 40. The range of ZQ is 210 to 270, giving an output impedance range of 35 to 45 (one sixth the value of ZQ within 10%). RES, CLK and CLK are not internally terminated. The value of ZQ is used to calibrate the internal DQ termination resistors of DQ<0:31>, WDQS<0:3> and
VDDQ ZQ/4 or ZQ/2 Terminator when receiving
Read to other Rank
Output Data Read Data Enable DQ
ZQ/6 Driver when transmitting
VSSQ
Figure 6 Table 11 Parameter
Output Driver simplified schematic Range of external resistance ZQ Symbol ZQ min 210 nom 240 max 270 Unit Notes
External resistance value Table 12 Ball CLK, CLK, RDQS<0:3>, ZQ, RES
Termination types and activation Termination type No termination Add / CMDs DQ DQ Always ON Always ON CMD bus snooping Termination activation
CKE, CS, RAS, CAS, WE, BA<0:1>, A<0:11> DM<0:3>, WDQS<0:3>, DQ<0:31>
Data Sheet
24
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.3.2
Self Calibration for Driver and Termination
Figure 7 Table 13 Parameter
Termination update keep out time after Autorefresh command Termination update Keep Out time Symbol -1.6 min max -- min 10 Limit Values -2.0 max -- min 10 -2.2 max -- ns Unit Notes
Termination update Keep Out time
tKO
10
To guarantee optimum driver impedance after power-up, the GDDR3 SGRAM needs 350 cycles after the clock is applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 350 cycles, but optimal output impedance will not be guaranteed. The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration : The PMOS device is calibrated against the external ZQ resistor value (Figure 8). First one PMOS leg is calibrated against ZQ. The number of legs used for the terminators ( DQ and ADD/CMD) and the PMOS driver is represented in Table 14. Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses 6 NMOS legs. Table 14 Number of Legs used for Terminator and Driver Self Calibration Termination CKE (at RES) Terminator ADD / CMD 0 1 EMRS[3:2] DQ 00 10 11 Driver PMOS NMOS Disabled ZQ/4 ZQ/2 ZQ/6 ZQ/6 0 4 2 6 6 1 ZQ/2 ZQ 2 1 Number of Legs Notes
Note: EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
Data Sheet
25
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description Figure 8 represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted in such a way that the VDDQ voltage is divided equaly between the PMOS device and the ZQ resistor. The best bit pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET is calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause the comparator to switch the NMOS Match signal output value.
VDDQ
VDDQ
Strength Control [2:0]
VSSQ
NMOS Calibration
PMOS Calibration
Match VDDQ / 2
ZQ Match VDDQ / 2 VSSQ
Strength Control [2:0]
VSSQ
Figure 8
Self Calibration of PMOS and NMOS Legs
3.3.3
Dynamic Switching of DQ terminations
The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and command terminators are always enabled.
Data Sheet
26
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Functional Description
Figure 9
ODT Disable Timing during a READ command
3.3.4
Output impedance and Termination DC Electrical Characteristics
The Driver and Termination impedances are determined by applying VDDQ/2 nominal (1.0 V) at the corresponding input / output and by measuring the current flowing into or out of the device. VDDQ is set to the nominal value of 2.0 V. (see Table 1)
IOH is the current flowing out of DQ when the Pull-Up transistor is activated and the DQ termination disabled. IOLis the current flowing into DQ when the Pull-Down transistor is activated and the DQ termination disabled. ITCAH(ZQ) is the current flowing out of the Termination of Commands and Addresses for a ZQ termination value.
Table 15 Parameter ZQ Value DC Electrical Characteristics Nom. 240 min max 25.0 25.0 4.2 mA mA mA 1 1 1 20.5 20.5 3.4 Unit
Notes
IOH IOL ITCAH(ZQ)
ZQ/6 ZQ/6 ZQ
Note: 1: Measurement performed with VDDQ =2.0 V (nominal see Table 1) and by applying VDDQ/2 (1.0 V) at the corresponding Input / Output. 0C TC 85C.
Data Sheet
27
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HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.4
Extended Mode Register Set Command (EMRS)
The Extended Mode Register is used to set the output driver impedance value, the termination impedance value, the Write Recovery time value for Write with Autoprecharge. It is used as well to enable/disable the DLL, to issue the Vendor ID and to enable/disable the Low Power mode. There is no default value for the Extended Mode Register. Therefore it must be written after power up to operate the GDDR3 Graphics RAM. The Extended Mode Register can be programmed by performing a normal Mode Register Set operation and setting the BA0 bit to HIGH. All other bits of the EMR register are reserved and should be set to LOW. The Extended Mode Register must be loaded when all banks are idle and no burst are in progress. The controller must wait the specified time tMRD before initiating any subsequent operation). The timing of the EMRS command operation is equivalent to the timing of the MRS command operation.
Figure 10
Extended Mode Register Bitmap
Figure 11
Extended Mode Register Bitmap
1. Autocalibration is not supported for these settings. 2. Default termination values at Power Up. Data Sheet 28 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description 3. The ODT disable function disables all terminators on th device. 4. If the user activates bits in an extended mode register in an optional field, either the optional field is activated (if option implemented on the device) or no action is taken by the device (if ioption not implemented). 5. WR (write recovery time for write with autoprecharge) in clock cycles is calculated by dividing tWR (in ns) and rounding up to the next integer (WR[cycles]=tWR[ns]/tCK[ns]). The mode register must be programmed to this value.
Figure 12 Table 16 Parameter
Extended Mode Register Set Timing EMRS Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max -- min 4 Limit Values -2.0 max -- min 4 -2.2 max -- Unit Notes
Mode Register Set cycle time
tMRD
5
tCK
3.4.1
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is enabled automatically). Anytime the DLL is enabled, 200 cycles must occur before a READ command can be issued.
3.4.2
WR
The WR parameter is programmed using the register bits A4 and A5. This integer parameter defines as a number of clock cycles the Write Recovery time in a Write with Autoprecharge operation. The following inequality has to be complied with : WR * tCK tWR, where tCK is the clock cycle time as defined in Table 8 and tWR the Write Recovery time as defined in Table 23. Note: Refer to Figure 3.7.4 for more details.
3.4.3
Termination Rtt
The data termination, Rtt , is used to set the value of the internal terminaton resistors. The GDDR III DRAM supports ZQ / 4 and ZQ / 2 termination values. The termination may also be disabled for testing and other purposes.
3.4.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance. When the autocalibration is used, the output driver impedance is set nominally to ZQ / 6.
Data Sheet
29
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.4.5
Low Power
When the Low Power extended mode register is set, the device enters a low power mode of operation. This mode is not enabled for the HYB18T256324F-[16/20/22]. Setting this bit to HIGH will have no effect on the behavior of the GDDR3 DRAM.
3.4.6
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the Infineon vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a new EMRS command is issued with A10 set back to 0. After tRDoff following the second EMRS command, the data bus is driven back to HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this requirement will result in unspecified operation. Table 17 DQ[7:4] 0001 Revision ID and Vendor Code Infineon Vendor Code DQ[3:0] 0010
Revision Identification
Note: Please refer to Revision Release Note for Revision ID value
Figure 13 Table 18 Parameter
Timing of Vendor Code and Revision ID generation on DQ[7:0] Vendor Code and Revision ID Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max 20 20 min -- -- Limit Values -2.0 max 20 20 min -- -- -2.2 max 20 20 ns ns Unit Notes
EMRS to DQ on time EMRS to DQ off time
tRIDon tRIDoff
-- --
Data Sheet
30
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.5
Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of the memory. It programs read latency, test mode, DLL Reset and the value of the write latency. There is no default value for the mode register; therefore it must be written after power up to operate the GDDR3 Graphics RAM. During a Mode Register Set command the address inputs are sampled and stored in the mode register. tMRD must be met before any command can be issued to the Graphics SDRAM. The Mode Register contents can only be set or changed when the Graphics SDRAM is in idle state.
Figure 14
Mode Register Set Command
Figure 15
Mode Register Bitmap
Note: The DLL Reset command is self-clearing Data Sheet 31 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
Figure 16 Table 19 Parameter
Mode Register Set Timing MRS Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max -- -- min 4 12 Limit Values -2.0 max -- -- min 4 12 -2.2 max -- -- tCK tCK 1, 2 1 Unit Notes
Mode Register Set cycle time Mode Register Set to READ timing
tMRD tMRDR
5 15
1. This value of tMRD applies only to the case where the "DLL reset" bit is not activated. 2. tMRD is defined from MRS to any other command as READ.
3.5.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length 4. This value must be programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block if a boundary is reached. The block is uniquely selected by A2-Ai where Ai is the most significant bit for a given configuration. The starting location within this block is determined by the two least significant bits A0 and A1 which are set internally to the fixed value of zero each. Reserved states should not be used, as unknow operation or incompatibility with future versions may result.
3.5.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3) . This device does not support the burst interleave mode. Table 20 Burst Type Starting Column address A1 A0 xx 0-1-2-3 Order of accesses within the burst Type = Sequential 4
Burst Length
The value applied at the balls A0 and A1 for the column address is "Don't care".
Data Sheet
32
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.5.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data as shown on Figure 31. The latency can be set to 5 to 7 clocks as shown in Figure 15. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally concident with clock edge n+m. Refer to Appendix, Figure 42, for values of operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
3.5.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data as shown in Figure 21. WL can be set from 2 to 4 clocks depending on the operating frequency. Setting the WRITE latency to 2 or 3 clocks will cause the device to enable the data input receivers on all ACT commands.
3.5.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and A8-A11 set to the desired value.
3.5.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 SGRAM returns automatically in the normal mode of operations once the DLL reset is completed.
Data Sheet
33
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.6
Bank / Row Activation (ACT)
Before a READ or WRITE command can be issued to a bank, a row in that bank must be opened. This is accomplished via the ACT command, which selects both the bank and the row to be activated. After opening a row by issuing an ACT command, a READ or WRITE command may be issued after tRCD to that row. A subsequent ACT command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACT commands to the same bank is defined by tRC. A subsequent ACT command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACT commands to different banks is defined by tRRD. There is a minimum time tRAS between opening and closing a row.
Figure 17
Activating a specific row
Figure 18
Bank Activation timing
Data Sheet
34
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
Table 21 Parameter
ACT Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max -- 8 x tREFI -- -- min 37.2 24.0 8.0 16.0 Limit Values -2.0 max -- 8 x tREFI -- -- min 39.6 26.2 8.8 17.5 -2.2 max -- 8 x tREFI -- -- ns ns ns ns ns Unit Notes
Row Cycle Time Row Active Time ACT(a) to ACT(b) Command period Row to Column Delay Time for Reads Row to Column Delay Time for Writes
tRC tRAS tRRD tRCDRD tRCDWR
37.2 24.0 8.0 16.0
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK(min)
3.7 3.7.1
Writes (WR) Write Basic Information
Write bursts are initiated with a WR command, as shown in Figure 19. The column and bank addresses are provided with the WR command, and Auto Precharge is either enabled or disabled for that access. The length of the burst initiated with a WR command is always four. There is no interruption of WR bursts. The two least significant address bits A0 and A1 are 'Don't Care'. For WR commands with Autoprecharge the row being accessed is precharged tWR/A after the completion of the burst. If tRAS(min) is violated the begin of the internal Autoprecharge will be performed one cycle after tRAS(min) is met. tWR/A can be programmed in the Mode Register. Choosing high values for tWR/A will prevent the chip to delay the internal Autoprecharge in order to meet tRAS(min). During WR bursts data will be registered with the edges of WDQS. The write latency can be programmed during Extended Mode Register Set. The first valid data is registered with the first valid rising edge of WDQS following the WR command. The externally provided WDQS must switch from HIGH to LOW at the beginning of the preamble. There is also a postamble requirement before the WDQS returns to HIGH. The WDQS signal can only transition when data is applied at the chip input and during pre- and postambles.
Figure 19
Write Command
tDQSS is the time between WR command and first valid rising edge of WDQS. Nominal case is when WDQS edges are aligned with edges of external CLK. Minimum and maximum values of tDQSS define early and late WDQS operation. Any input data will be ignored before the first valid rising WDQS transition. tDQSL and tDQSH define the width of low and high phase of WDQS. The sum of tDQSL and tDQSH has to be tCK.
35 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
Data Sheet
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description Back to back WR commands are possible and produce a continuous flow of input data. There must be one NOP cycle between two back to back WR commands. Any WR burst may be followed by a subsequent RD command. Figure 3.7.5 shows the timing requirements for a WR followed by a RD. A WR may also be followed by a PRE command to the same bank. tWR has to be met as shown in Figure 3.7.8. Table 22 WDQS WDQS0 WDQS1 WDQS2 WDQS3 Mapping of WDQS and DM signals Data mask signal DM0 DM1 DM2 DM3 Controlled DQs DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 Setup and hold time for incoming DQs and DMs relative to the WDQS edges are specified as tDS and tDH. DQ and DM input pulse width for each input is defined as tDIPW. The input data is masked if the corresponding DM signal is high. All timing parameters are defined with graphics DRAM terminations on.
Figure 20
Basic Write Burst / DM Timing
Note: : WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
36
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
Table 23 Parameter
WR Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max -- min 2 Limit Values -2.0 max -- min 2 -2.2 max -- Unit Notes
CAS(a) to CAS(b) Command period Write command to first WDQS latching transition
tCCD tDQSS
2 WL 0.25 0.35 0.35 0.45 0.45 0.45 0.75 0.75 6.0
tCK
1)
Write Cycle Timing Parameters for Data and Data Strobe WL WL +0.25 0.25 -- -- -- -- -- 1.25 1.25 -- WL WL +0.25 0.25 WL tCK +0.25 ns ns
2)
Data-in and Data Mask to WDQS Setup tDS Time Data-in and Data Mask to WDQS Hold Time
0.375 -- 0.375 -- 0.45 0.45 0.45 0.75 0.75 6.0 -- -- -- 1.25 1.25 --
0.375 -- 0.375 -- 0.45 0.45 0.45 0.75 0.75 6.6 -- -- -- 1.25 1.25 --
tDH
2)
Data-in and DM input pulse width (each tDIPW input) WDQS input low pulse width WDQS input high pulse width WDQS Write Preamble Time WDQS Write Postamble Time Write to Read Command Delay
tCK tCK tCK tCK tCK
ns
3) 3)
2)4) Write Recovery Time 11.0 -- 11.0 -- 11.0 -- ns 1) tCCD is either for gapless consecutive writes or gapless consecutive reads 2) Timing parameters defined with Graphics DRAM terminations on. 3) tDQSL. and tDQSH apply for the Write preamble and postamble as well. 4) tWTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQSx signal
tDQSL tDQSH tWPRE tWPST tWTR tWR
2)4)
Data Sheet
37
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.2
Write - Basic Sequence
Figure 21 1. 2. 3. 4.
Write Burst Basic Sequence
Shown with nominal value of tDQSS. WDQS can only transition when data is applied at the chip input and during pre- and postambles. When NOPs are applied on the command bus, the WDQS and the DQ busses remain stable High. When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown. 38 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
Data Sheet
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.3 3.7.3.1
Write - Consecutive Bursts Gapless Bursts
Figure 22
Gapless Write Bursts
1. Shown with nominal value of tDQSS 2. The second WR command may be either for the same bank or another bank 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
39
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.3.2
Bursts with Gaps
Figure 23
Consecutive Write Bursts with Gaps
1. Shown with nominal value of tDQSS. 2. The second WR command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
40
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.4
Write with Autoprecharge
Figure 24 1. 2. 3. 4.
Write with Autoprecharge
Shown with nominal value of tDQSS tWR/A starts at the first rising edge of CLK after the last valid edge of WDQS. tRP starts after tWR/A has been expired. when issuing a WR/A command please consider that the tRAS requirement also must be met at the beginning of tRP 5. tWR/A * tCYC tWR 6. WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
41
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.5
Write followed by Read
Figure 25
Write followed by Read
1. Shown with nominal value of tDQSS. 2. The RD command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
42
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.6
Write followed by DTERDIS
Figure 26
Write Command followed by DTERDIS
1. Write shown with nominal value of tDQSS. 2. WDQS can only transition when data is applied at the chip input and during pre- and postambles 3. A margin of one clock has been introduced in order to make sure that the data termination are still on when the last Write data reaches the memory. 4. The minimum distance between Write and DTERDIS is (WL -CL + 4) clocks and always bigger than or equal to 1. For (CL=6 / WL=2) and (CL=7 / WL=3) as well as for (CL=7 / WL=2) the minimum distance between Write and DTERDIS is set to 1 clock. Please refer to table below: Table 24 WL \ CL 2 3 4 Data Sheet WL / CL 5 1 2 3 6 1 1 2 43 7 1 1 1 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.7
Write with Autoprecharge followed by Read / Read with Autoprecharge
Figure 27 1. 2. 3. 4.
Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank
Shown with nominal value of tDQSS. The RD command is only allowed for another activated bank tWR/A is set to 3 in this example WDQS can only transition when data is applied at the chip input and during pre- and postambles 44 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
Data Sheet
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.7.8
Write followed by Precharge on same Bank
Figure 28 1. 2. 3. 4.
Write followed by Precharge on same Bank
Shown with nominal value of tDQSS. WR and PRE commands are to same bank tRAS requirement must also be met before issuing PRE command WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
45
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8 3.8.1
Reads (RD) Read - Basic Information
During RD bursts the memory device drives the read data edge aligned with the RDQS signal which is also driven by the memory. After a programmable CAS latency of 5, 6 or 7 the data is driven to the controller. RDQS leaves HIGH state one cycle before its first rising edge (RD preamble tRPRE). After the last falling edge of RDQS a postamble of tRPST is performed.
tAC is the time between the positive edge of CLK and the appearance of the corresponding driven read data. The skew between RDQS and the crossing point of CLK/CLK is specified as tDQSCK. tAC and tDQSCK are defined relatively to the positive edge of CLK. tDQSQ is the skew between a RDQS edge and the last valid data edge belonging to the RDQS edge. tDQSQ is derived at each RDQS edge and begins with RDQS transition and ends with the last valid transition of DQs. tQHS is the data hold skew factor and tQH is the time from the first valid rising edge of RDQS to the first conforming DQ going non-valid and it depends on tHP and tQHS. tHP is the minimum of tCL and tCH. tQHS is effectively the time from the first data transition (before RDQS) to the RDQS transition. The data valid window is derived for each RDQS transition and is defined as tQH minus tDQSQ.
After completion of a burst, assuming no other commands have been initiated, data will go High-Z and RDQS will go HIGH. Back to back RD commands are possible producing a continuous flow of output data. There has to be one NOP cycle between back to back RD commands. Any RD burst may be followed by a subsequent WR command. The minimum required number of NOP commands between the RD command and the WR command (tRTW) depends on the programmed Read latency and the programmed Write latency tRTW(min)= (CL+4-WL) Chapter 3.8.5 shows the timing requirements for RD followed by a WR with some combinations of CL and WL. A RD may also be followed by a PRE command. Since no interruption of bursts is allowed the minimum time between a RD command and a PRE is two clock cycles as shown in Chapter 3.8.6. All timing parameters are defined with controller terminations on.
Figure 29
Read Command
Read bursts are initiated with a RD command, as shown in Figure 29. The column and bank addresses are provided with the RD command and Autoprecharge is either enabled or disabled for that access. The length of the burst initiated with a RD command is always four. There is no interruption of RD bursts. The two least significant start address bits are 'Don't Care'. If Autoprecharge is enabled, the row being accessed will start precharge at the completion of the burst. The begin of the internal Autoprecharge will always be one cycle after tRAS(min) is met.
Data Sheet
46
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
Figure 30
Basic Read Burst Timing
1. The GDDR3 SGRAM switches off the DQ terminations one cycle before data appears on the busand drives the data bus HIGH. 2. The GDDR3 SGRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching the termination on again. Table 25 Parameter READ Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min CAS (a) to CAS (b) Command period Read to Write command delay Data Access Time from Clock Read Preamble Read Postamble max -- min 2 Limit Values -2.0 max -- min 2 -2.2 max -- tCK tCK 0.45 1.25 1.25 ns Unit Note
tCCD tRTW tAC tRPRE tRPST
2
1
2 4
tRTW(min)= (CL+4-WL) -0.4 0.75 0.75 0.4 1.25 1.25 -0.4 0.75 0.75 0.4 1.25 1.25 -0.45 0.75 0.75
Read Cycle Timing Parameters for Data and Data Strobe
tCK tCK
4 4 4 4 4 4 3
Data-out high impedance time from CLK tHZ Data-out low impedance time from CLK tLZ RDQS edge to Clock edge skew RDQS edge to output data edge skew Data hold skew factor Data output hold time from RDQS Minimum clock half period 1. 2. 3. 4.
tACmin tACmin
-0.4 -- 0
tACmax tACmin tACmax tACmin
0.4 -0.4 0.225 -- 0.225 0
tACmax tACmin tACmax tACmin
0.4 -0.45 0.225 -- 0.225 0
tACmax ns tACmax ns
0.45 0.25 0.25 -- ns ns ns ns
tDQSCK tDQSQ tQHS tQH tHP
tHP-tQHS
0.45 --
tHP-tQHS
0.45 --
tHP-tQHS
0.45
tCK
tCCD is either for gapless consecutive reads or gapless consecutive writes. Please round up tRTW to the next integer of tCK. tHP is the minimum of tCL and tCH Timing parameters defined with controller terminations on.
47 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
Data Sheet
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8.2
Read - Basic Sequence
Figure 31
Read Burst
1. Shown with nominal tAC and tDQSQ 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data
Data Sheet
48
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8.3 3.8.3.1
Consecutive Read Bursts Gapless Bursts
Figure 32 1. 2. 3. 4.
Gapless Consecutive Read Bursts
The second RD command may be either for the same bank or another bank Shown with nominal tAC and tDQSQ Example applies only when READ commands are issued to same device RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS 5. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data
Data Sheet
49
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8.3.2
Bursts with Gaps
Figure 33
Consecutive Read Bursts with Gaps
1. The second RD command may be either for the same bank or another bank 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data
Data Sheet
50
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8.3.3
Read followed by DTERDIS
Figure 34
Read Command followed by DTERDIS
1. At least 3 NOPs are required between a READ command and a DTERDIS command in order to avoid contention on the RDQS bus in a 2 rank system. 2. CAS Latency 5 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of (BL/2 + 2 ) clocks. 4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case, RDQS would be driven by the second Graphics DRAM.
Data Sheet
51
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8.4
Read with Autoprecharge
Figure 35
Read with Autoprecharge
1. When issuing a RD/A command , the tRAS requirement must be met at the beginning of Autoprecharge 2. Shown with nominal tAC and tDQSQ 3. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS 4. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data 5. tRAS Lockout support
Data Sheet
52
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8.5
Read followed by Write
Figure 36
Read followed by Write
1. Shown with nominal tAC, tDQSQ and tDQSS 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data 4. WDQS can only transition when data is applied at the chip input and during pre- and postambles 5. The Write command may be either on the same bank or on another bank
Data Sheet
53
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.8.6
Read followed by Precharge on the same Bank
Figure 37 1. 2. 3. 4.
Read followed by Precharge on the same Bank
tRAS requirement must also be met before issuing PRE command RD and PRE commands are applied to the same bank. Shown with nominal tAC and tDQSQ RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS
Data Sheet
54
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.9
Data Termination Disable (DTERDIS)
The Data Termination Disable command is detected by the device by snooping the bus for Read commands when CS is high. The terminators are disabled starting at CL - 1 clocks after the DTERDIS command is detected and the duration is 4 clocks. The command and address terminators are always enabled. DTERDIS may only be applied to the GDDR3 Graphics memory if it is not in the Power Down or in the Self Refresh state. The timing relationship between DTERDIS and other commands is defined by the constraint to avoid contention on the RDQS bus (i.e Read to DTERDIS transistion) or the necessity to have a defined termination on the data bus during Write (i.e. Write to DTERDIS transition). ACT and PRE/PREALL may be applied at any time before or after a DTERDIS command.
Figure 38
Data Termination Disable Command
Figure 39
DTERDIS Timing
Data Sheet
55
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
Figure 40
DTERDIS followed by DTERDIS
1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transistion on the other memory in a 2 rank system. 2. CAS Latency 5 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of (BL/2 + 2 ) clocks 4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case, RDQS would be driven by the second Graphics DRAM.
Data Sheet
56
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.9.1
DTERDIS followed by READ
Figure 41
DTERDIS Command followed by READ
1. At least 3 NOPs are required between a DTERDIS command and a READ command in order to avoid contention on the RDQS bus in a 2 rank system. 2. CAS Latency 5 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4 clocks.
Data Sheet
57
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.9.2
DTERDIS followed by Write
Figure 42
DTERDIS Command followed by Write
1. Write shown with nominal value of tDQSS 2. WDQS can only transition when data is applied at the chip input and during pre- and postambles 3. The minimum distance between DTERDIS and Write is (CL -WL + 4) clocks.
Data Sheet
58
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.10
Precharge (PRE/PREALL)
The Precharge command is used to deactivate the open row in a particular bank (PRE) or the open rows in all banks (PREALL). The bank(s) will enter the idle state and be available again for a new row access after the time tRP. A8/AP sampled with the PRE command determines whether one or all banks are to be precharged. For PRE commands BA0 and BA1 select the bank. For PREALL inputs BA0 and BA1 are "Don't Care". The PRE/PREALL command may not be given unless the tRAS requirement is met for the selected bank (PRE), or for all banks (PREALL).
Figure 43 Table 26 A8 / AP 0 0 0 0 1
Precharge Command BA1, BA0 precharge bank selection BA1 0 0 1 1 X BA0 0 1 0 1 X precharged bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All banks
Data Sheet
59
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
Figure 44 Table 27 Parameter
Precharge Timing Precharge Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max - min 13.2 Limit Values -2.0 max - min 13.2 -2.2 max - ns Unit Notes
Row Precharge Time
tRP
13.2
Data Sheet
60
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.11
Auto Refresh Command (AREF)
AREF is used to do a refresh cycle on one row in each bank. The addresses are generated by an internal refresh controller; external address pins are "DON'T CARE". All banks must be idle before the AREF command can be applied. The delay between the AREF command and the next ACT or subsequent AREF must be at least tRFC(min). The refresh period starts when the AREF command is entered and ends tRFC later at which time all banks will be in the idle state. Within a period of tREF=32ms the whole memory has to be refreshed. The average periodic interval time from AREF to AREF is then tREFI(max)=7.8s. To improve efficiency bursts of AREF commands can be used. Such bursts may consist of maximum 8 AREF commands. tRFC(min) is the minimum required time between two AREF commands inside one AREF burst. According to the number of AREF commands in one burst the average required time from one AREF burst to the next can be increased. Example: If the AREF bursts consists of 4 AREF commands, the average time from one AREF burst to the next is 4 * 7.8s = 31.2s. The AREF command generates an update of the OCD output impedance and of the addresses, commands and DQ terminations. The timing parameter tKO ( see section 2.3.2 ) must be complied with.
Figure 45
Auto Refresh Command
Figure 46 Table 28 Parameter
Auto Refresh Cycle Autorefresh Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max 32 7.8 54 -- 54 min -- Limit Values -2.0 max 32 7.8 -- 54 min -- -2.2 max 32 7.8 -- ms s ns Unit Notes
Refresh Period (4096 cycles) Average periodic Auto Refresh interval Delay from AREF to next ACT/ AREF
tREF tREFI tRFC
--
Data Sheet
61
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.12 3.12.1
Self-Refresh Self-Refresh Entry (SREFEN)
The Self-Refresh mode can be used to retain data in the GDDR3 Graphics RAM even if the rest of the system is powered down. When in the Self-Refresh mode, the GDDR3 Graphics RAM retains data without external clocking. The Self-Refresh command is initiated like an Auto-Refresh command except CKE is disabled (LOW). Self Refresh Entry is only possible if all banks are precharged and tRP is met. The GDDR3 Graphics RAM has a build-in timer to accomodate Self-Refresh operation. The Self-Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the command is registered, CKE must be held LOW to keep the device in Self-Refresh mode. When the GDDR3 Graphics RAM has entered the SelfRefresh mode, all external control signals, except CKE are disabled. The address, command and data terminators remain on. The DLL and the clock are internally disabled to save power. The user may halt the external clock while the device is in Self-Refresh mode the next clock after Self-Refresh entry, however the clock must be restarted before the device can exit SelfRefresh operation.
Figure 47
Self Refresh Entry Command
Figure 48
Self Refresh Entry
Data Sheet
62
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.12.2
Self-Refresh Exit (SREFEX)
To exit the Self Refresh Mode, a stable external clock is needed before setting CKE high asynchronously. Once the Self-Refresh Exit command is registered, a delay equal or longer than tXSC (minimum 200 Clock Cycles) must be satisfied before any command can be applied. During this time, the DLL is automatically enabled, reset and calibrated. CKE must remain HIGH for the entire Self-Refresh exit period and commands must be gated off with CS held HIGH. Alternately, NOP commands may be registered on each positive clock edge during the Self Refresh exit interval.
Figure 49
Self Refresh Exit Command
Figure 50 Table 29 Parameter
Self Refresh Exit Self Refresh Exit Timing Parameter for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max - min 200 Limit Values -2.0 max - min 200 -2.2 max - Units Notes
Self Refresh Exit time
tXSC
200
tCK
Data Sheet
63
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Functional Description
3.13
Power-Down
burst completion is defined after the rising edge of the Read Postamble. For Writes, a burst completion is defined one clock after the rising edge of the Write Postamble. For Read with Autoprecharge and Write with Autoprecharge, the internal Autoprecharge must be completed before entering Power-Down. Power-Down is entered when CKE is registered LOW (no access can be in progress). If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power-Down occurs when there is a row active in any bank, this mode is referred to as Active Power-Down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE. For maximum power saving, the user has the option of disabling the DLL prior to entering power-down. In that case the DLL must be enabled and reset after exiting power-down, and 200 cycles must occur before a READ command can be issued. In Power-Down mode, CKE low and a stable clock signal must be maintained at the inputs of the GDDR3 Graphics RAM, all the other input signals are "Don't Care". Power down duration is limited by the refresh requirements of the device. The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESEL command). A valid executable command may be applied tXPN later.
Figure 51
Power Down Command
Unlike SDR SDRAMs, the GDDR3 Graphics RAM requires CKE to be active at all times an access is in progress : From the issuing of a READ or WRITE command until completion of the burst. For READs, a
Figure 52 Table 30 Parameter
Power-Down Mode Power Down Exit Timing Parameter for -1.6, -2.0 and -2.2 speed sorts Symbol -1.6 min max -- Limit Values -2.0 min 4 max -- -2.2 min 4 max -- Unit Notes
Precharge power-down exit timing
tXPN
5
tCK
Data Sheet
64
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4
4.1
Table 31 Parameter
Electrical Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings Symbol Rating min. max. 2.5 2.5 V V V V C mA -0.5 -0.5 -0.5 -0.5 -55 -- Unit
Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Storage Temperature Short Circuit Output Current
VDD VDDQ VIN VOUT TSTG IOUT
VDDQ+0.5 VDDQ+0.5
+150 50
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32 Parameter Operation Temperature (Junction) Operation Temperature (Case) Power Dissipation Operation Conditions Symbol Range min. max. +90 +85 3.2 C C W 0 0 -- Unit
TJ TC PD
Data Sheet
65
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.2
Recommended Power & DC Operation Conditions.
All values are recommended operating conditions unless otherwise noted. Tc = 0 to 85 C. (0C TC +85C, VDD = +2.0 V 0.10 V, VDDQ = +2.0 V 0.10 V, see Table 1) Table 33 Parameter Power Supply Voltage Power & DC Operation Conditions Symbol Speed sort Limit Values min. 1.9 1.9 1.9 1.9 1.9 1.9 typ. 2.0 2.0 2.0 2.0 2.0 2.0 max. 2.1 2.1 2.1 2.1 2.1 2.1 V V V V V V
1) 1) 1) 1) 1) 1) 2) 2)3) 2)3)
Unit Notes
VDD
-1.6 -2.0 -2.2
Power Supply Voltage for I/O Buffer
VDDQ
-1.6 -2.0 -2.2
Reference Voltage
VREF
-1.6 -2.0 -2.2
0.72*VDDQ 0.73*VDDQ 0.74*VDDQ V 0.72*VDDQ 0.73*VDDQ 0.74*VDDQ 0.72*VDDQ 0.73*VDDQ 0.74*VDDQ 0.4*VDDQ -5 -5 -5 +5 +5 +5 V
A A A
Output Low Voltage Input leakage current CLK Input leakage current Output leakage current
1)
VOL(DC) IIL IILC IOL
4)
4)
VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 2) VREF is allowed 19mV for DC error and an additionnal 28mV for AC noise. 3) VREF is expected to equal 73% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% VREF (DC). Thus, from 73% of VDDQ. 4) IIL and IOL are measured with ODT disabled.
Data Sheet
66
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.3
DC & AC Logic Input Levels.
(0C TC +85C, VDD = +2.0 V 0.10 V, VDDQ = +2.0 V 0.10 V, see Table 1) Table 34 Parameter Input logic high voltage, DC Input logic low voltage, DC Input logic high voltage, AC Input logic low voltage, AC Input logic high, DC, RESET pin Input logoc low, DC, RESET pin DC & AC Logic Input Levels Symbol Limit Values min. max. -- 0.7 *VDDQ -0.15 -- 0.7 *VDDQ - 0.4 V V V V V V 1 1 2,3 2,3 0.7 *VDDQ + 0.15 -- 0.7 *VDDQ +0.4 -- 0.8 *VDDQ -0.3 Unit Notes
VIH(DC) VIL(DC) VIH (AC) VIL(AC) VIHR(DC) VILR(DC)
VDDQ + 0.3
0.2 *VDDQ
1. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. 2. Input slew rate = 2 V/ns. If the input slew rate is less than 2 V/ns, input timing may be compromised. All slew rates are measured between VIL(DC) and VIH(DC). 3. VIH overshoot : VIH(MAX) = VDDQ+0.5 V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = 0 V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
4.4
Differential Clock DC and AC Levels
(0C TC +85C, VDD = +2.0 V 0.10 V, VDDQ = +2.0 V 0.10 V, see Table 1) Table 35 Parameter Differential Clock DC and AC Input conditions Symbol Limit Values min. Clock Input Mid-Point Voltage, CLK and CLK VMP(DC) Clock Input Voltage Level, CLK and CLK max. Unit Note s 1 1 1 1, 2 1, 3
VREF - 0.1
0.42 0.3 0.5
VIN(DC)
Clock DC Input Differential Voltage, CLK and VID(DC) CLK Clock AC Input Differential Voltage, CLK and VID(AC) CLK AC Differential Crossing Point Input Voltage VIX(AC)
VREF + 0.1 VDDQ + 0.3 VDDQ VDDQ + 0.5 VREF + 0.15
V V V V V
VREF - 0.15
1. All voltages referenced to VSS 2. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. 3. The value of VIX is expected to equal 0.7 x VDDQ of the transmitting device and must track variations in the DC level of the same.
Data Sheet
67
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.5
Output Test Conditions
VDDQ
60 Ohm
DQ DQS
Test point
Figure 53
Output Test Circuit
Note: VDDQ=2.0 0.1 V, Tc=0 C to 85 C, see Table 1
4.6
Table 36 Parameter
Pin Capacitances
Capacitances Symbol CCK CDCK CI DCI CIO 2.5 2.0 Min 2.0 Max 4.0 0.1 4.0 0.6 4.5 Unit pF pF pF pF pF 1 1 Notes
Input capacitance: CLK, CLK Input capacitance delta: CLK, CLK Input capacitance: A0-A11, BA0-1,CKE, CS, CAS, RAS, WE, CKE, RES Input capacitance delta: A0-A11, BA0-1,CKE, CS, CAS, RAS, WE, CKE, RES Input capacitance: DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0DM3 Input capacitance delta: DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0DM3
DCIO
0.6
pF
2
1. The input capcitance per pin group will not differ by more than this maximum amount for any given device. 2. The IO capacitance per RDQS and DQ byte / group will not differ by more than this maximum amount for any given device.
Data Sheet
68
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.7 4.7.1
Driver current characteristics Driver IV characteristics at 40 Ohms
Figure 54 represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature best and worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240, setting the nominal driver output impedance to 40.
Figure 54
40 Ohm Driver Pull-Down and Pull-Up characteristics
Table 37 lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down and Pull-Up IV characteristics. Table 37 Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Data Sheet Programmed Driver IV Characteristics at 40 Ohm Pull-Down Current (mA) Minimum 2.32 4.56 6.69 8.74 10.70 12.56 14.34 16.01 17.61 19.11 20.53 21.92 23.29 24.65 26.00 27.35 28.70 Maximum 3.04 5.98 8.82 11.56 14.19 16.72 19.14 21.44 23.61 26.10 28.45 30.45 32.73 34.95 37.10 39.15 41.01 42.53 43.71 69 Pull-Up Current (mA) Minimum -2.44 -4.79 -7.03 -9.18 -11.23 -13.17 -15.01 -16.74 -18.37 -19.90 .21.34 -22.72 -24.07 -25.40 -26.73 -28.06 -29.37 Maximum -3.27 -6.42 -9.45 -12.37 -15.17 -17.83 -20.37 -22.78 -25.04 -27.17 -29.17 -31.25 -33.00 -35.00 -37.00 -39.14 -41.25 -43.29 -45.23 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.8
Termination IV Characteristic at 60 Ohms
Figure 55 represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual DQ termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240, setting the nominal DQ termination impedance to 60. (Extended Mode Register programmed to ZQ/4).
Figure 55
60 Ohm Active Termination Characteristic
Table 38 lists the numerical values of the minimum and maximum allowed values of the output driver termination IV characteristic. Table 38 Voltage (V) Programmed Terminator Characterisitc at 60 Ohm Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -1.63 -3.19 -4.69 -6.12 -7.49 -8.78 -10.01 -11.16 -12.25 Maximum 1.0 -2.18 -4.28 -6.30 -8.25 -10.11 -11.89 -13.58 -15.19 -16.69 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Voltage (V) Terminator Pull-Up Current (mA) Minimum -13.27 -14.23 -15.14 -16.04 -16.94 -17.82 -18.70 -19.58 Maximum -18.11 -19.45 -20.83 -22.00 -23.33 -24.67 -26.09 -27.50 -28.86 -30.15
Data Sheet
70
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.9
Termination IV Characteristic at 120 Ohms
Figure 56 represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240, setting the nominal termination impedance to 120. (Extended Mode Register programmed to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during Power-Up for ADD/CMD terminations).
Figure 56
120 Ohm Active Termination Characteristic
Table 39 lists the numerical values of the minimum and maximum allowed values of the termination IV characteristic. Table 39 Voltage(V) Programmed Terminator Characterisitics at 120 Ohm Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -0.81 -1.60 -2.34 -3.06 -3.74 -4.39 -5.00 -5.58 -6.12 Maximum 1.0 -1.09 -2.14 -3.15 -4.12 -5.06 -5.94 -6.79 -7.59 -8.35 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Voltage (V) Terminator Pull-Up Current (mA) Minimum -6.63 -7.11 -7.57 -8.02 -8.47 -8.91 -9.35 -9.79 Maximum -9.06 -9.72 -10.42 -11.00 -11.67 -12.33 -13.05 -13.75 -14.43 -15.08
Data Sheet
71
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.10
Termination IV Characteristic at 240 Ohms
Figure 57 represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240, setting the nominal termination impedance to 240. (CKE = 1at the RES transition during Power-Up for ADD/CMD terminations).
Figure 57
240 Ohm Active Termination Characteristic
Table 40 lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV characteristic. Table 40 Voltage (V) Programmed Terminator Characterisitc at 240 Ohm Terminator Pull-Up Current (mA) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -0.41 -0.80 -1.17 -1.53 -1.87 -2.20 -2.50 -2.79 -3.06 Maximum 1.0 -0.55 -1.07 -1.58 -2.06 -2.53 -2.97 -3.40 -3.80 -4.17 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Voltage (V) Terminator Pull-Up Current (mA) Minimum -3.32 -3.56 -3.79 -4.01 -4.23 -4.46 -4.68 -4.90 Maximum -4.53 -4.86 -5.21 -5.50 -5.83 -6.17 -6.52 -6.88 -7.21 -7.54
Data Sheet
72
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.11 4.11.1
Operating Currents Operating Current Ratings
(0C TC +85C, VDD = +2.0 V 0.10 V, VDDQ = +2.0 V 0.10 V, see Table 1) Table 41 Parameter Operating Current Operating Current Precharge Power-Down Standby Current Precharge Floating Standby Current Precharge Quiet Standby Current Active Power-Down Standy Current Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRC=min(tRFC)) Auto-Refresh Current at tREFI Self Refresh Current Operating Current
1)
Operating Current Ratings Symbol -1.6 typ. -2.0 typ. 238 258 86 136 98 86 158 412 278 374 88 11 548 -2.2 typ. 222 241 81 127 92 81 148 385 265 348 83 11 509 mA mA mA mA mA mA mA mA mA mA mA mA mA
1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3)4) 1)2)3)
Unit
Notes
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
274 297 99 156 113 99 182 474 320 430 101 11 630
IDD specifications are tested after the device is properly initialized.
2) Input slew rate = 2 V/ns. 3) Mesured with Output open and On Die termination off. 4) Enables on-chip refresh and address counter.
4.12
Operating Current Measurement Conditions
(0C TC +85C, VDD = +2.0V 0.10 V, VDDQ = +2.0 V 0.10 V, see Table 1) Table 42 Operating Current Measurement Conditions Operating Current - One bank, Activate - Precharge tCK=min(tCK), tRC=min(tRC) Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between valid commands. Operating Current - One bank, Activate - Read - Precharge One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are SWITCHING; CS = HIGH between valid commands. Iout=0mA Precharge Power-Down Standby Current All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE. Precharge Floating Standby Current All banks idle; CS is LOW, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING; Data bus input are STABLE.
Symbol Parameter/Condition
IDD0
IDD1
IDD2P IDD2F
Data Sheet
73
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics Table 42 Operating Current Measurement Conditions Precharge Quiet Standby Current CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE, Data bus inputs are STABLE. Active Power-Down Standby Current All banks active, CKE is LOW, Address and control inputs are STABLE; Data bus inputs are STABLE; standard active power-down mode. Active Standby Current All banks active, CS is HIGH, CKE is HIGH, tRC=max(tRAS), tCK=min(tCK); Address and control inputs are SWITCHING; Data bus inputs are SWITCHING; Iout = 0 mA. Operating Current - Burst Read All banks active; Continuous read bursts, CL = CL(min); tCK=min(tCK); Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. Operating Current - Burst Write All banks active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING; Data bus inputs are SWITCHING. Burst Auto Refresh Current Refresh command at tRC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING. Distributed Auto Refresh Current tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING. Self Refresh Current CKE max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE; Data Bus inputs are STABLE. Operating Bank Interleave Read Current 1. All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0mA; Address and control inputs are STABLE during DESELECT; Data bus inputs are SWITCHING. 2: Timing pattern: -1.6 (600 MHz, CL=7) : tCK = 2.5ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D TBD TBD TBD -2.0 (500 MHz, CL7) : tCK = 2.0ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D -2.2 (455 MHz, CL6) : tCK = 2.2ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
Symbol Parameter/Condition
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1. Data Bus consists of DQ, DM, WDQS 2. Definitions for IDD : LOW is defined as VIN = 0.4 x VDDQ; HIGH is defined as VIN = VDDQ; STABLE is defined as inputs are stable at a HIGH level. SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals, and inputs changing 50% of each data transfer for DQ signals. 3. Legend : A=Activate, RA=Read with Autoprecharge, D=DESELECT
Data Sheet
74
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.13
Summary of timing parameters for -1.6, -2.0 and -2.2 ns speed sorts in DLL on mode
Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Read Symlatency bol Limit Values -1.6 min max 3.3 3.3 -- 600 500 -- 0.55 0.55 -- -- -- -- min 2.0 2.0 -- 250 250 -- 0.45 0.45 0.45 0.75 0.75 0.85 -2.0 max 4.0 4.0 -- 500 500 -- 0.55 0.55 -- -- -- -- min 2.2 2.2 2.7 250 250 250 0.45 0.45 0.45 0.75 0.75 0.85 -2.2 max 4.0 4.0 4.0 455 455 370 0.55 0.55 -- -- -- -- ns ns ns MHz MHz MHz Unit Notes
Table 43 Parameter
Clock and Clock Enable Clock Cycle Time 7 6 5 System frequency 7 6 5 Clock high level width Clock low-level width Minimum clock half period
tCK7 tCK6 tCK5 fCK7 fCK6 fCK5 tCH tCL tHP
1.6 2.0 -- 300 300 -- 0.45 0.45 0.45 0.6 0.6 0.85
tCK tCK tCK
ns ns
1)
Command and Address Setup and Hold Timing Address/Command input setup time tIS Address/Command input hold time Address/Command input pulse width Mode Register Set Timing Mode Register Set cycle time Row Timing
tIH tIPW
tCK
tMRD Mode Register Set to READ timing tMRDR tRC Row Active Time tRAS ACT(a) to ACT(b) Command period tRRD Row Precharge Time tRP Row to Column Delay Time for tRCDRD
Row Cycle Time Reads Row to Column Delay Time for Writes Column Timing CAS(a) to CAS(b) Command period tCCD Write to Read Command Delay Read to Write command delay Write command to first WDQS latching transition Data-in and Data Mask to WDQS Setup Time
5 15 37.2 24.0 8.0 13.2 16.0
-- -- -- 8 x tREFI -- -- --
4 12 37.2 24.0 8.0 13.2 16.0
-- -- -- -- - -
4 12 39.6 8.8 13.2 17.5
-- -- -- -- - -
tCK tCK
ns ns ns ns ns
8 x tREFI 26.2
8 x tREFI ns
tRCDWR
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK(min)
2 6.0
-- --
2 6.0
-- --
2 6.6
-- --
tCK
ns
2) 3) 4)
tWTR tRTW tDQSS tDS
tRTW(min)= (CL+4-WL) WL 0.25 0.35 WL +0.25 -- WL 0.25 0.375 WL +0.25 -- WL 0.25 0.375 WL +0.25 --
tCK tCK
ns
Write Cycle Timing Parameters for Data and Data Strobe
Data Sheet
75
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics Table 43 Parameter Timing Parameters for -1.6, -2.0 and -2.2 speed sorts Read Symlatency bol Limit Values -1.6 min Data-in and Data Mask to WDQS Hold Time Data-in and DM input pulse width (each input) DQS input low pulse width DQS input high pulse width DQS Write Preamble Time DQS Write Postamble Time Write Recovery Time Data Access Time from Clock max -- -- -- -- 1.25 1.25 -- 0.4 1.25 1.25 min 0.375 0.45 0.45 0.45 0.75 0.75 11.0 -0.4 0.75 0.75 0.35 0.45 0.45 0.45 0.75 0.75 11.0 -0.4 0.75 0.75 -2.0 max -- -- -- -- 1.25 1.25 -- 0.4 1.25 1.25 min 0.375 0.45 0.45 0.45 0.75 0.75 11.0 -0.45 0.75 0.75 -2.2 max -- -- -- -- 1.25 1.25 -- 0.45 1.25 1.25 ns Unit Notes
tDH tDIPW tDQSL tDQSH tWPRE tWPST tWR
tCK tCK tCK tCK tCK
ns ns 3
Read Cycle Timing Parameters for Data and Data Strobe
tAC Read Preamble tRPRE Read Postamble tRPST Data-out high impedance time from tHZ
CLK Data-out low impedance time from CLK DQS edge to Clock edge skew
tCK tCK
ns ns ns ns ns ns ms s
tACmin tACmin
-0.4 -- 0
tACmax tACmax
0.4 0.225 0.225
tACmin tACmin
-0.4 -- 0
tACmax tACmax
0.4 0.225 0.225
tACmin tACmin
-0.45 -- 0
tACmax tACmax
0.45 0.25 0.25
tLZ
tDQSCK DQS edge to output data edge skew tDQSQ Data hold skew factor tQHS Data output hold time from DQS tQH tREF tREFI tRFC tXSC tXPN t XARD tATS tATH tKO tRIDon tRIDoff
tHP-tQHS
-- 7.8 54 200 5 8 10 10 10 -- -- -- -- -- -- -- -- -- 20 20 32
tHP-tQHS
-- 7.8 54 200 4 6 10 10 10 -- -- -- -- -- -- -- -- -- 20 20 32
tHP-tQHS
-- 7.8 54 200 4 6 10 10 10 -- -- -- -- -- -- -- -- -- 20 20 32
Refresh/Power Down Timing Refresh Period (4096 cycles) Average periodic Auto Refresh interval Delay from AREF to next ACT/ AREF Self Refresh Exit time Precharge Power Down Exit time Active Power Down Exit time Other Timing Parameters RES to CKE setup timing RES to CKE hold timing Termination update Keep Out timing Rev. ID EMRS to DQ on timing Rev. ID EMRS to DQ off timing
1) 2)
ns
tCK tCK tCK
ns ns ns ns ns
tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs tCCD is either for gapless consecutive reads or gapless consecutive writes. 3) tWTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal. 4) Please round up tRTW to the next integer of tCK.
Data Sheet 76 Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Electrical Characteristics
4.14
AC Characteristics and Settings
The following tables are meant as a guideline to correctly set the most important timing parameters depending on speed sort and clock frequency. Table 44 HYB18T256324F-16 CAS tRC Latency 7 7 7 6 6 6 23 19 17 15 14 12
Frequency / tCK 600 MHz / 1.6ns 500 MHz / 2.0ns 455 MHz / 2.2ns 400 MHz / 2.5ns 370 MHz / 2.7ns 300 MHz / 3.0ns Table 45
tRFC
33 27 25 22 20 17
tRAS
15 12 11 10 9 8
tRP
8 7 6 6 5 4
tWR
7 6 5 5 5 4
tRRD
5 4 4 4 3 3
tRCDRD
10 8 8 7 6 5
tRCDWR Unit
7 6 6 5 5 4
tCK tCK tCK tCK tCK tCK
HYB18T256324F-20 CAS tRC Latency 7 7,6 7,6 6 6 19 17 15 14 12
Frequency / tCK 500 MHz / 2.0ns 455 MHz / 2.2ns 400 MHz / 2.5ns 370 MHz / 2.7ns 300 MHz / 3.0ns Table 46
tRFC
27 25 22 20 17
tRAS
12 11 10 9 8
tRP
7 6 6 5 4
tWR
6 5 5 5 4
tRRD
4 4 4 3 3
tRCDRD
8 8 7 6 5
tRCDWR Unit
5 5 4 4 3
tCK tCK tCK tCK tCK
HYB18T256324F-22 CAS tRC Latency 7 7,6 7,6 5 5 5 18 16 15 12 11 10
Frequency / tCK 455 MHz / 2.2ns 400 MHz / 2.5ns 370 MHz / 2.7ns 300 MHz / 3.0ns 266 MHz / 3.8ns 250MHZ / 4.0ns
tRFC
25 22 20 17 15 14
tRAS
12 11 10 8 7 7
tRP
6 6 5 4 4 4
tWR
5 5 5 4 3 3
tRRD
4 4 4 3 3 3
tRCDRD
8 7 7 6 5 5
tRCDWR Unit
5 5 4 4 3 3
tCK tCK tCK tCK tCK tCK
Data Sheet
77
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Package Outlines
5
Package Outlines
11.00 0.10
BALL A1 INDICATOR
11.00 0.10
1.20 MAX
TOP VIEW C
1
2
3
4
5
6
7
8
9 10 11 12
M L K
H G F E D C B A
0.40
J
0.80 (11X)
0.10
C
0.12
C
0.40 0.80 (11X)
BALLS VIEW
All dimensions in mm.
Figure 58
Package Outline FBGA
1. The package is conforming with JEDEC MO216 2. The inner matrix of 4x4 balls is reserved for thermal contacts
Data Sheet
78
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
HYB18T256324F-[16/20/22] 256-Mbit DDR SGRAM
Package Outlines
5.1
Table 47
Package Thermal Characteristics
P-FBGA 144 Package Thermal Resitances Theta_jA Theta_jB 2s0p 3 m/s 35.1 0 m/s 27.0 1 m/s 23.5 3 m/s 22.0 6.0 3.9 Theta_jC 1s0p 0 m/s 48.8 1 m/s 40.2
JEDEC Board Air Flow K/W
1. Theta_jA : Junction to Ambient thermal resistance. The values have been obtained by simulation using the conditions stated in the JEDEC JESD-51 standard. 2. Theta_jB : Junction to Board thermal resistance. The value has been obtained by simulation. 3. Theta_jC : Junction to Case thermal resistance. The value has been obtainned by simulation.
Data Sheet
79
Rev. 1.11, 04-2005 10292004-DOXT-FS0U
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Published by Infineon Technologies AG

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